Agner`s CPU blog

• The prefix byte 62 is now used for the AVX512 instruction set extensions
  
• A few AMD instructions are now copied by Intel, including RDTSCP, LZCNT, and PREFETCHW
  
• The obsolete AMD-only instructions that are not copied by Intel are no longer supported by the latest AMD processors. This includes the 3DNow, XOP, and FMA4 instruction set extensions.
  
• The old obsolete and undocumented Intel instructions are still supported by both Intel and AMD processors
  
• There is now more than 2000 instructions in the x86 instruction set with its many extensions
  
• Planned instruction set extensions are now published by Intel quite early so that programmers can prepare to use them, but not early enough to respond to suggestions from the public
  

Due to the problems discussed in this thread, I have taken the initiative to develop a completely new instruction set that is open and license-free. This new instruction set is called Forwardcom. It has variable-length vector registers, and it is forward compatible in the sense that software written for one implementation of a Forwardcom processor will run optimally without re-compilation on later versions with longer vector registers. Forwardcom is neither RISC nor CISC but combining the best from both technologies. It has relatively few instructions but many variants of each instruction. See www.forwardcom.info for details.