Here is an update of instructions that were first announced by AMD and later
copied by Intel:
| Instruction name |
AMD instruction set |
Intel instruction set |
Compatible |
Remark |
| prefetch |
3DNow |
SSE |
no |
Intel name: prefetcht0, etc. |
| 64 bit mode |
AMD64 |
Intel 64 |
yes |
|
| rdtscp |
SSE4A |
(AVX) |
yes |
Separate CPUID bit |
| lzcnt |
SSE4A |
future AVX2 |
yes |
|
| vpshld, etc. |
SSE5/XOP |
future AVX2 |
no |
Intel name: vpsllvd, etc. |
| cvtph2ps, cvtps2ph |
SSE5/XOP |
future |
no |
|
| vfmaddps, etc. |
SSE5/XOP |
FMA3 |
no |
Both AMD and Intel have changed their codes.
Final version is
incompatible |
While AMD keeps copying almost all Intel instructions (except virtualization
instructions) for the sake of compatibility, only few of AMDs instructions are
copied by Intel. In those cases where Intel have copied an AMD instruction using
the XOP coding scheme, they have made an incompatible code using the VEX coding
scheme. |
Stop the instruction set war new - Agner Fog - 2009-12-05
The instruction set war's effect on virtualization new - Yuhong Bao - 2009-12-28