Agner`s CPU blog

The decoder can do 2-1-1 or 1-1-1-1

Let me go straight on example:
XCHG a,b
TEST c,c
MOV r,[m]
is 2-1-1, decode in one cycle (i took last mov in AGU, as you reported)
ADD a,b
ADD c,d
MOV s,[m]
MOV d,[m]
is a 1-1-1-1 and still decode in ONE cycle?
How can the first decode choose if it should fetch one or two instructions (maybe l1 tag too?), and even in such case, how's possible it can decode two instructions...