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Test results for Intel's Sandy Bridge processor
Author: Agner Date: 2013-08-08 01:38
anon wrote:
Repeating 6 not/neg (2 or 3 bytes x 6) will be affected by predecoder's limitation.
Is there a limitation on decoding short instructions? Is this documented anywhere?
I have observed on the Haswell that conditional move instructions, which generate 2 microops, decode at two per clock only when I add prefixes to make the instructions 4 bytes long. This applies also when the microop cache is used.
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