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Test results for Intel's Sandy Bridge processor
Author: Agner Date: 2013-08-09 01:53
This looks like an alignment issue. The code is fetched in 16-bytes blocks. Instructions that cross a 16-bytes boundary (or 32-bytes boundary?) are decoded less efficiently. The 發p cache is coupled to the instruction cache with a maximum of three 6-發p entries per 32 bytes block of code. How this translates to inefficiency when instructions with certain lengths execute out of the 發p cache, I don't really understand.

I have done some experiments to test your claim that fuseable instructions decode less efficiently:

xchg r8,r9    ; 3 發ps. Decodes alone
or eax,eax    ; 1 發p, D0
or ebx,ebx    ; 1 發p, D1
or ecx,ecx    ; 1 發p, D2
or edx,edx    ; 1 發p, D3
This decodes in 2 clocks. If the last OR is changed to an AND, it decodes in 3 clocks. It will not put a fuseable arithmetic/logic instruction in decoder D3 because then it can't check in the same clock cycle if the next instruction is a branch. There is no effect when this executes out of the 發p cache.
 
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