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Test results for Intel's Sandy Bridge processor
Author: Agner Date: 2013-10-10 10:34
Thank you for your comments John.

I think it is unlikely that the cache could be running at double clock frequency. It is too big for that. Some previous models have run the cache at half clock frequency. Maybe your observations have something to do with the fact that the Sandy Bridge has two read ports?

Have you tried on Haswell? It should have no cache bank conflicts

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