Agner`s CPU blog

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Optimization manuals updated - Silvermont test
Author: Tacit Murky Date: 2014-08-11 07:33
Hi, Agner.
You've mentioned, that there's only one L1D cache access port, which can be a serious bottleneck. However, according to your timing table, "ADD m,r" instruction is fully pipelined, that can only be explained by 2 ports (read+write) working simultaneously. AIDA64's InstLat readout supports this -- see instlatx64.atw.hu for "Bay Trail" or "Avoton" cores. Moreover, unaligned reads and even writes (up to 16 B) are pipelined as well. What are your results for unaligned accesses?

Descriptions of "partial OoO" and other things are here: www.realworldtech.com/silvermont/ . Kanter usually gets such info directly from design team.

 
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