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Micro-fusion limited to 1-reg addressing modes
Author: Agner Date: 2015-12-01 09:07
Peter Cordes wrote:
uop micro-fusion on Intel SnB seems to be possible only when it doesn't create uops with more than 2 input dependencies.
I have now tested this on Sandy Bridge, Ivy Bridge, Haswell and Broadwell. I have not had access to test on a Skylake yet.

The results show that instructions with three input dependencies are fusing alright and use only a single entry in the micro-operation cache, unless they contain more than 32 bits of address and immediate data. Instructions with more than 32 bits of data are still fusing, but use two entries in the micro-operation cache. It is possible to make instructions with four input dependencies on Haswell and Broadwell, using the fused multiply-and-add instructions. These are still fusing alright and use only a single entry in the micro-operation cache.

Instructions with both rip-relative addressing and immediate data do not fuse.
The results are identical on the four machines tested.

 
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