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Proposal for an ideal extensible instruction set
Author:  Date: 2016-01-05 10:47
Re: vector length issues:

Various folks at Berkeley have been looking at flexible vector architectures for microprocessors. A search for Krste Asanovic and vectors should point you at much of the recent work.
Their proposals have long included reconfigurable vector registers -- allowing a block of SRAM to be divided into different configurations of vector length vs number of vectors.
More recent proposals would allow the elements of different vectors to be of different sizes.

Asanovic has argued for an ISA that would allow decoupling the vector width from the parallelism of the underlying hardware, so a single binary could have its vector instructions pipelined through whatever number of "vector pipelines" an implementation happened to provide. The presentation slides are at riscv.org/workshop-jun2015/riscv-vector-workshop-june2015.pdf

I like the ideas, but have not looked at them in enough detail to form an opinion about their practicality.

I can say that I am getting very tired of trying to work around the limitations of existing SIMD vector ISAs. They are great when everything is lined up, but in that case you are almost always bandwidth-limited so the extra functional units don't help. They are a real pain when the data in the registers needs to be rearranged, which is the most common way that physics-based codes generate computational intensity.

 
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