Agner`s CPU blog

I have no problem with using "word" to mean 32 bits and "halfword" for 16 bits.

Regarding code density. The problems with 16-bit instructions are many. You can't have 3-register instructions. You don't have space for specifying operand size and type, vector size, predicate or mask, rounding mode, exception handling, and all the other features that may be needed in the future. And quite importantly: memory address offsets and immediate constants have odd sizes in a 16-bit coding scheme. This causes problems in linkers and loaders when the offsets overflow, and it causes problems for the high-level language programmer who may not know whether a constant will fit into an instruction.

With a 16-bit minimum instruction word size, you will waste more bits for specifying instruction size. And instruction decoding will be a bottleneck like it is in x86. The nice thing about my proposal of 32-bit instruction words is that it allows a completely orthogonal instruction set. Any instruction can be specified with a register operand or a memory operand or an immediate operand - all with the same size, so that you can be certain that any value will fit into any of these, while small values can still be fit into smaller instructions to save code cache space.

If code density is important, then I can suggest a compromise. Allow two tiny instructions to fit into a 32-bit code word. The first 4 bits of the 32-bit word indicate that this is a double instruction, followed by two tiny instructions of 14 bits each. These tiny instructions obviously don't need any bits for specifying instruction size. They can be used for the most common simple instructions with one or two registers. A disadvantage is that you cannot jump to the second instruction of such a pair of tiny instructions. All jump offsets are still scaled by the standard instruction word size of 4 bytes.

Regarding your proposal of pipelined "string" instructions. They will have to either include memory addresses and work on the level-1 cache or use a register stack of fixed size. If your code has multiple accumulators or vectors then you need multiple register stacks. This sounds quite complicated to me. I am not sure I understand your idea.