Agner`s CPU blog

- It makes bank selection for loads more complex, potentially increasing load latency by a cycle (presumably from 3 cycles to 4 cycles with address calculation included) due to having more multiplexers on address inputs on each bank, more multiplexers on writebacks, more different stalling scenarios and probably requiring an increase in the number of banks.

- It makes load/store address conflict detection harder since you need to check even more reads against pending writes in the write buffer, and deal with more scenarios like multiple reads trying to access forwarded store values.

I've played around with various concepts to deal with this but I'm not sure I've found anything really interesting yet:

- A L0 cache could be introduced. Probably something very small, single-way, duplicated multiple times, probably loading whole cache lines from L1 on every miss and probably only used when there are too many loads per cycle to be satisfied by the L1. Problems: this is still limited to 1 store per cycle, filling values from L1 competes with stores for the single write port, doesn't simplify address conflict detection with the store queue. (if I'm not mistaken, GPUs use something like this?)

- Pointers could be stored in special registers, and when a pointer register is updated, data from nearby addresses (say, possibly something like adr+0 to adr+63) are automatically pre-read into registers, and there is an automatic check that none of the other pointer registers are pointing to the same data with data modifications. You would possibly also have load/store instructions that bypass these special pointer registers (but with address conflict checking). This is very complex (especially the address checking, which is unfortunately necessary for C++ compilers), and it doesn't help you at all if your data is widely spaced or uses indexed offsets (register+register*n). But on the other hand, data accesses that do fall into this pattern (like loading/storing a whole bunch of contiguous stack addresses or object member variables) become register accesses, they can be renamed, reordered willy-nilly, pretty much every instruction can load/store a value, misaligned addresses don't matter anymore (except when changing a pointer register), and if the address is divisible by 64 you can conceivably load/store a whole cache line in one go.