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Proposal for an ideal extensible instruction set
Author: Hubert Lamontagne Date: 2016-03-08 12:39
Joe Duarte: Looking up transport-triggered-architectures.... They are interesting but I think they share most problems with VLIW:

Programs typically look kinda like this:
- Load from memory #1
- Long chain of dependent math #1
- Store to memory #1
- Load from memory #2
- Long chain of dependent math #2
- Store to memory #2

To run in parallel, you have to run the math chain #1 and #2 at the same time. Since chain #2 ops depend on load #2, you have to move load #2 up before store #1. This forces the compiler to prove that load #2 and store #1 can't possibly fall on the same memory address (this is what the LLVM alias analysis does), which turns out to be a hard problem often requiring global analysis and often fails. VLIW architectures often have software alias detection to deal with this: the Transmeta Crusoe had Load-Lock, Store-Check, Commit(+jump to fallback if commit fails); Itanium infamously had the ALAT where you'd do a ld.a (advanced load), then later on a ld.c or chk.a to confirm that the data from the ld.a isn't baloney and branch to fallback code if it is.

Out-of-order architectures are popular because they do this automatically for you (the store operations calculate the target address on the spot but can wait for the value for many cycles). Also, what if a load doesn't fall into L1 cache? On a VLIW (and, presumably, TTA, unless you made all your transport use queues), this is a hard stall. Out-of-order architectures can at least somewhat reorder operations around this - with some luck, hopefully it can find enough operations to do until it can get an L2 cache result.

Other problem is, as Agner said, that it's hard to adapt code written for a gen 1 TTA cpu to some presumably larger gen 2 TTA cpu - you'd probably need to more or less dynamically recompile it to the new wider cpu, which is easily as complex as current out-of-order RISCs and ARMs and x86s.

That being said, supposedly NVidia's Denver pulls off VLIW correctly and gives good perf, so I guess it is possible to make this work.

---

For built-in constants, that's not so useful because a lot of constants also have some scaling built-in (for instance result = sin(2.f * 3.141592653f / 256.f * i); ) and most of the time if your calculation involves pi or e, it involves some very slow op like sin() or exp() so having to load one more constant from cache won't slow down things appreciably.

 
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