Agner`s CPU blog

Paging also removes the need for segmentation, which is why it's so popular - as far as I know it's still a net gain in simplicity.

I guess the potential avenues for simplification are:

- By making the pages very large, you could perhaps make the page table small enough to fit in on-chip static RAM, which would make the state machine for loading the TLB simpler. Probably not worth the trouble but still an interesting concept.

- You could debate removing page fault exceptions. This would keep the "heap memory management" aspect of paging (and probably the "security" aspect by mapping unauthorized accesses to a dummy page), but would make it impossible to implement virtual memory (aka disk swapping) and other similar tricks (file memory mapping etc). The benefit is that instructions following a load/store are no longer speculative, which could probably be beneficial on some semi-out-of-order architectures (for instance, having load addresses generated on the FPU with an FPU running super late in the pipeline).