Agner`s CPU blog

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Proposal now published
Author: Agner Date: 2016-03-25 05:04
Hubert Lamontagne wrote:
I'm really curious about how the hardware would be able to do that mapping in a very short time (ideally in a single
cycle, and in a way that the L1 cache data lines that get read don't depend on virtual address translation).
The virtual address translation is just an adder in the memory map that I am envisaging, rather than the multi-level table lookup of a traditional TLB. You may put virtual address translation after the L1 cache to make cache access faster.

The memory map is saved and restored on a task switch since there will be a separate memory map for each process.

It has many other parts that would be more complex or would require microcode.
I hope not. I would rather have more complexity in the pipeline and perhaps dedicated state machines to things like interrupts and system calls rather than using microcode. Microcode seems to be incredibly slow in the processors I have tested, though I don't know exactly why.

Well, "load register and increment pointer" writes to 2 registers so it's similar in complexity to "load dual".
Pop dual will write 3 registers, including the stack pointer. I think a fixed limit of two output registers is fair. We need that for flags output anyway.

I just checked msvc's x64 output, and I'm admit I'm very spooked. It does stuff like loading an index into eax, then using rax as an array index, even though the variable is clearly signed in the code. Some code locations seem to use movsx for sign extension, but most don't.
In my experiment, the MS compiler sign-extended the index outside a loop, the Gnu compiler used zero-extension. Gcc is (in-)famous for interpreting standards in a very pedantic way. There is probably some C standard saying that a negative index to a pointer or array is undefined.
 
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