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Do we need instructions with two outputs?
Author: Hubert Lamontagne Date: 2016-04-07 23:32
Joe Duarte wrote:
Hubert said:
- 3-bytes can't be aligned to cache lines. If you have an array of pointers, eventually one of the pointers has to straddle 2 cache lines and that's a much larger penalty than some wasted DCache due to using 4-byte pointers.

- 3-bytes is only a 16 Mb address space, and few languages want to be limited to something that small. You cannot start with 3-byte pointer program and then dynamically upgrade everything to 4-bytes if you ever run out of space. Might as well make everything 4-byte from the start.

You're assuming byte-addressable memory. I'm assuming that these pointers or references would point to memory objects of arbitrary size, determined by what the variable, object, or function needs. I don't see why a program can't just tag its objects and entities in a virtual memory space with clean and compact pointers (but without garbage collection – just virtual memory.) I feel like there's not enough *virtual* in virtual memory right now – we should be able to abstract more.
Okay, but how do you get the individual fields out of the object you've got the reference of? Then you need both the object's handle/tag/reference/id, and an offset from the start of the object data (traditionally in bytes), or at least some kind of field ID (but that adds yet another translation pass to get the real byte offset).

The other issue is that you're probably going to hammer the TLB a lot harder that way: you're making the TLB hold all your real pointers instead of just page remaps. Which means you'll probably need a bigger, more complex TLB.

Third, this doesn't play well with C++ specifically, because objects aren't necessarily housed within their own memory allocation, they can be contained inside a larger object, or inside an array, or on the stack. So you need to save not only the handle, but also the byte offset. This is essentially the same thing as the infamous FAR pointer from 16-bit x86 coding.

Joe Duarte wrote:
https://www.irisa.fr/alf/downloads/rohou/doc/Rohou_CGO11.pdf

On the issue of a Rx register, I think it might be a useful abstraction in some cases. You said that CPUs do this already, that we don't know what register we're getting. Yet, we're still naming registers explicitly, and you find it useful to retain named registers in an ISA. There are benefits to have named architectural registers, and I think there would be benefits from anonymous register semantics. Hubert asked how we'd refer back to it. There would be rules about how such register semantics could be used, and how to manage them – they wouldn't be the same as the normal registers. There are few ways to go about it.

Then you've either got a register stack like the 8087 fpu or some ultra-low-power CPUs (GreenArrays chips, designed to run Forth), or a queue like in the Mill (which it calls the "belt") or the Itanium rotating register file, depending on if your system forgets the newest values after use or the oldest ones.
 
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