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Do we need instructions with two outputs?
Author: Hubert Lamontagne Date: 2016-04-09 00:06
HarryDev wrote:
Hi, related to the JIT discussion I think the proposed ISA needs specific instruction for memory copying, initialization and comparison. Especially, memory copying from small number of bytes to big is important in GC related scenarios. Often memory copy ends up being implemented as multiple complicated vector instructions, when an ISA instruction would be so much better (the CPU could then handle this in the most optimized way for it). Some research has been done on this where adding "cpblk", "initblk" instructions where evaluated and these showed great benefit for code size and speed. I would allow these instructions to have element size defined i.e. 1, 2, 4, 8, 16 bytes for example so one can initialize a "double" array quickly, perhaps even a zero out "zeroblk" instruction since this is used a lot in managed memory scenarios.
That's why x86 has the 'string copy' etc instructions. And the speed gain depends on the CPU generation...:

- On 8086 / 80286 / 80386, loading instructions was slow (no instruction cache!), so they string instructions were the fastest indeed. Other CPUs of the time also have stuff like this: z80 has string copies too, as does 65816, and 68000 has move multiple.

- On 486 and Pentium, designers realized that non-microcoded instructions can be implemented to run a lot faster, but there was only so much space on chips so only few instructions could get the speedup, so string instructions were left out and actually ran slower... RISC CPUs don't have any string copy instructions either - it just doesn't fit in their design!

- On later out-of-order x86 CPUs, string copies are still microcoded so they're slow to start, but once started they do wide multibit copies. So the end result is similar to the multiple complicated vector instructions anyways (since CPUs still have to deal with alignment). On the latest Ivy bridge and Haswell, string copy instructions are now the same speed as software loops - but that's a new thing: on preceding architectures, string copy instructions are still slower... RISC architectures like ARM mostly went with vector instructions to fill this need.

So I'm not sure that string copy/zero/compare instructions are still relevant nowadays because memory bandwidth is not all that fast, and the kind of pointer updating that was costly on 8 and 16 bit CPUs is now free since it runs in ALUs in parallel while the data cache does its job. And having CPU string copy instructions doesn't remove the need for complex cacheline-aligned loops - it's really just moving that complexity from the software to the microcode. I think it would be better to look into garbage collection algorithms that don't do compaction and don't recopy everything (and an end to Java's "allocate humongous blocks of memory on startup" approach).

 
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