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Proposal for an ideal extensible instruction set
Author: Hubert Lamontagne Date: 2016-04-11 21:03
There is an algo for doubling the precision of floating point adding:

Kahan summation


A-11 wrote:

It should be too late.
but since I found a research today, I ask for it.

BOOST: Berkeley's Out-of-Order Stack Thingy
https://www.researchgate.net/publication/228556746_BOOST_Berkeley's_Out-of-Order_Stack_Thingy

Same as "register renaming" for register machine, these researcher propose "address renaming" for stack machine to implement out-of-order execution.
So I think there are no reasons to prevent stack machine for performance problem.
Since stack machine instruction sets never bother us with number of registers, I think stack machine's ISA is more extensible than register machine's.
Also, stack ISA is easer for compilers as UCSD p-System showed.
it should also hold true for Just In-time Compiling.

That's an interesting architecture. Though I'm not sure I like how it's basically doing 2 or 3 memory accesses per cycle but then removing these accesses out using aggressive renaming, and that the stack and function-local memory accesses seem to not totally consistent with the "real" memory loads/stores through pointers. (otherwise it would have to stall every time no?)

Come to think of it, are there other "not totally consistent" memory models that are useful, performance wise? (aside from the standard multi-core - with - memory-barriers - and-so-forth stuff)

The one thing I do like about stack based architectures is how they reduce the number of register file read/writes, and intuitively I'd be more interested into a model that (1) also has registers (ie it's not using the stack to store values but rather to keep track of very short lived temporary values - and it has the nice property that the lifespan of values is well known) (2) has a limited stack stack depth - something like 16 values with no automatic spilling (ie just enough for calculations, function calls would still be done using the normal RISC mechanism and explicit memory operations for register/stack spills) (3) you're supposed to keep the stack empty as often as possible so that the CPU can automatically figure out which sections it can run in parallel (each time the size falls to 0, that's a new parallelizable section).

 
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