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treating stack ISA as CISC architecure
Author:  Date: 2016-04-14 02:55
Above BOOST architecture converts each one stack instruction to corresponding one RISC-like micro code.
Since stack ISA is more fine than even load-store RISC ISA which puts opcode field and operand field together in a instrcution, BOOST generates more RISC-like micro code, requires more massive monster renaming unit than even RISC architecture.
I think this is the major difficulty of BOOST, same as RISC requires more instruction throughput than CISC.
Since each entry of reservation station in a conventional CISC machine handles "macro code" which represents read-modify-write sequence and generates several RISC-like micro code, CISC machines beat RISC machines.
I think the source of CISC power is such a powerful RS entry, which is toward a tiny microprocessor same as EDGE.
Explicit_Data_Graph_Execution - Wikipedia
en.wikipedia.org/wiki/Explicit_Data_Graph_Execution
This means more powerful macro code reduces more pressure on a renaming unit, thus exploits more performance.
For example, read-modify-read-modify-read-write macro ops such as below line is preferred to read-modify-write ops.
read [sp + 2] ; read [sp + 4] ; mul ; read [sp + 5] ; add ; load-from-heap ; write [sp + 2] ;
But you will see this one macro op is similar to a sequence of 7 instructions written in stack ISA.
Thus, I think stack ISA can treat as CISC architecture with instruction border marking unit.
Maybe algorithm like matching parentheses will be used at border marking.
Note that instruction border is determined by machine implementation, not by ISA like x86.
If a machine can't deal with big macro ops like above, its border marking unit can split stack ISA sequence to fit its macro ops.
read [sp + 2] ; read [sp + 4] ; mul ; //read-read-modify-(write to stack)
read [sp + 5] ; add ; //(read from stack)-read-modify-(write to stack)
load-from-heap ; write [sp + 2] ; //(read from stack)-read-write
Or, since simple stack machine (one issue, in-order) is so tiny that it may fit in a RS entry, you might be able to treat a block separated between jump instructions as one macro op.
 
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