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Instruction Throughput on Skylake
Author:  Date: 2016-07-17 14:14
Interesting results. Looks like it's about the number of renamed registers. Apparently, Hwl had lower TP restriction for renamer, and it was upgraded for Skl. This explains faster case for Hwl (more µops with less arguments each, but only up to certain point). Peak issue rate is still 4 fused µIPC from IDQ to rename, but 6 unfused µIPC (correspondent to up to 6 IPC) for retire for Skl. Hwl can't allow more than 5 unfused µIPC.
 
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