Agner`s CPU blog

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Stop the instruction set war
Author: Agner Fog Date: 2010-01-13 01:37
bitRAKE wrote:
Couldn't the instruction cache store an efficient post-decode encoding for instructions?
AMD stores instruction boundaries in the code cache in order to make decoding easier. Intel did the same in the old Pentium MMX, IIRC. I don't know why they are not doing this any more.

Another possiblity would be to completely remap the instructions to favor parallel decoding.
They did that in Itanium. But emulation of x86 is too slow. The CISC instruction set, while difficult to decode, has the advantage that it takes less space in the code cache.

Has Intel used instruction set changes to negatively impact competitors (i.e. publishing the second best while secretly working on the target design)?
I don't think they have ever deliberately published suboptimal instructions. They have failed to support AMD instructions, and they have changed from FMA4 to FMA3 for unknown reasons. FMA4 is obviously better than FMA3 from the programmer's point of view. There may be technical limitations that made them change to FMA3.
 
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