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Pentium Appendix H
Author:  Date: 2010-02-10 11:46
Intel once tried to hide some of the new features of the Pentium from x86 competitors by requiring an NDA to be signed in order for info to be disclosed. It was nicknamed Appendix H because it was mentioned in the Appendix H of the Pentium processor family developer's manuals. AMD was able to reverse-engineer the Pentium and offer the K5 with all of them except APIC, but Cyrix cheated and only implemented the 486 instruction set in it's 6x86 and disabled the CPUID instruction by default. In the 6x86L, DE and CX8 was implemented, and in the 6x86MX, they implemented the features TSC and MSR from the Pentium and CMOV and PGE from the P6, but no PSE or VME.
Centaur when it released the WinChip decided to again not implement PSE or VME. They also did not implement CMOV or PGE unlike Cyrix 6x86MX. They implemented MCE unlike Cyrix though. WinChip 2 added 3DNow!. Eventually Centaur was sold to VIA Technologies, and it retargeted the core to Socket 370 and the P6 bus and marketed it as the VIA C3, but the core was still virtually the same as before in features with the only difference being that Intel's MTRRs replaced Centaur's MCR and the addition of PGE. Even worse, by then, Windows 2000 was released in which the NTVDM crashed without VME, forcing VIA to provide a patch to NTVDM. It was only with Nehemiah that VIA finally began to really improve the core, with SSE replacing 3DNow!, and PSE and CMOV being implemented. With stepping 8 Nehemiah, VIA finally added VME, SEP, and PAT, catching up with the Pentium III.
Rise mP6 was even worse, with it only implementing TSC, CX8, and MMX.
Cyrix MediaGX implemented only 486 level features like 5x86 and 6x86, and MediaGXm implemented CX8, TSC, MSR, CMOV, and MMX. Later processors in that series of course added more features.
Transmeta was better, with the Crusoe implementing Pentium MMX features (I think) plus CMOV and later SEP.
You can see here also that the 586/686 distinction can be quite blurry too, with lots of processors implementing only some 686 features. Even Intel's own Pentium M did not support PAE at all in the original version (luckily the option of using PAE is separate from the option of using i686 instructions in most OSes). The long NOPs that was introduced with the P6 were troublesome too, with even VIA Nehemiah not implementing it.
By now, it should be clear that Appendix H did a lot more harm than good, and it was only because the CPU feature bits that was invented with the CPUID instruction that software can wade through the mess. Before then, software just tested for CPU generation (for example, the 386/486 was differed by the test for EFLAGS.AC. Unfortunately I read that the IBM 386SLC CPU was really a relabeled 486 with all 486 instructions but with it being modified so that this test detects a 386, for reasons relating to Intel licensing. And the NexGen Nx586 originally implemented only 386 features, but later a hypercode update allowed user-mode 486 instructions to be supported if an option was enabled, but no kernel-mode instructions which was used by NT 4.0 and later preventing it from running), which has been considered dead since the introduction of CPUID. In fact, Intel did not bother creating a feature bit for the long NOPs, which means that it has to be manually tested via software using the illegal opcode exception, which was even harder in kernel mode because Connectix/Microsoft Virtual PC when encountering them in kernel mode code pops a fatal error that forces a reset of the virtual machine!
I wrote this from the research I did, and I got most of the CPU features mentioned above from datasheets from datasheets.chipdb.org , if there is any errors please correct!
 
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