Agner wrote:
McCalpin is surprised because this will
"break the fundamental architectural
paradigm", and so am I. It will be quite
complicated to implement in hardware. I have wondered
what the purpose of these instructions was, and
McCalpin seems to have the answer. If these
instructions are implemented in a successor of Knights
Landing, they should be single micro-op because the
Knights Landing has poor performance of
microcode.The new instructions are supported in my
disassembler (objconv), but I am not sure about the
assembly notation.
The AVX-512-4VNNIW ( Vector Neural Network Instructions Word variable precision ) which will firstly appear on Kights Mill seems also to extend VDPP(S/D) into the same vector+SIMD philosophy, although using Words/Doublewords (very DSP-like on the use of a higher precision accumulator) instead of Single/Double. https://en.wikipedia.org/wiki/AVX-512#New_instructions_in_AVX-512_4FMAPS_and_4VNNIW |
Future instruction set: AVX-512 new - Agner - 2013-10-09
Future instruction set: AVX-512 new - Agner - 2013-10-26