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Test results for Broadwell and Skylake
Author:  Date: 2017-07-12 00:13
Slide from Intel: https://www.pcper.com/image/view/83900?return=node%2F68093
Also from that article, interesting to note that the reduced AVX clocks also depend on the type of instruction; presumably, this means that 256b integer AVX2 code won't be throttled, as opposed to 256b FP code.

Intel's optimization manual has also been updated, with more details: https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf

a 1MB L2 cache and an additional Intel AVX-512 FMA unit on port 5 which is available on some parts.

Since port 0 and port 1 are 256-bits wide, Intel AVX-512 operations that will be dispatched to port 0 will execute on both port 0 and port 1; however, other operations such as lea can still execute on port 1 in parallel. See the red block in Figure 2-3 for the fusion of ports 0 and 1.

Notice that, unlike Skylake microarchitecture for client, the Skylake Server microarchitecture has its front end loop stream detector (LSD) disabled.

The guide also provides an example on how to detect 1 or 2 FMA unit chips (section 13.20), which seems to compare shuffle+FMA throughput with FMA throughput (not detected via CPUID it seems :O).

Also interesting to note is that mixing 256b and 512b instructions causes the CPU to run in '512b port mode' (section 13.19), where the 256b instructions only the the throughput of the equivalent 512b instruction.

 
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