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Test results for Broadwell and Skylake
Author:  Date: 2017-07-19 06:52
- wrote:
https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf

Also interesting to note is that mixing 256b and 512b instructions causes the CPU to run in '512b port mode' (section 13.19), where the 256b instructions only the the throughput of the equivalent 512b instruction.

Also in 13.19 : "The maximum register width in the reservation station (RS) determines the 256 or 512 port scheme."
I guess this was the adopted solution for avoiding vector stalls on Port 1, when Port 0 is used under the Port 0+1 AVX-512 scheme, even though it puts a higher stress on Port 5 as said in the manual.
 
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