Agner`s CPU blog

The Software Optimization Guide for AMD Family 17h Processors has been published recently (http://support.amd.com/TechDocs/55723_SOG_Fam_17h_Processors_3.00.pdf). It states that the L1 cache can handle two 16B loads and one 16B store per cycle. However www.agner.org/optimize/microarchitecture.pdf under 19.17 states "The data cache has two 128-bit ports which can be used for either read or write. It can do two reads or one read and one write in the same clock cycle." On what data is this latter statement based?

In contrast to AMD's statements, I haven't been able to get more than 32B/c from the L1 cache, giving credibility to the statement found in www.agner.org/optimize/microarchitecture.pdf. But I'm not sure what exactly the problem is. Either each AVX load or store is split into two separate SSE uops, each of which requires a dedicated AGU access. In that case the number of AGUs (two) limit the achievable L1 bandwidth. Or the L1 cache has in fact only two 128-bit ports as stated in www.agner.org/optimize/microarchitecture.pdf