Vector Class Discussion

thread Implementation for Intel Xeon Phi ? - Wilfried KIRSCHENMANN - 2013-10-15
last replythread Implementation for Intel Xeon Phi ? - Agner - 2013-10-15
last replythread Implementation for Intel Xeon Phi ? - Sylvain Collange - 2013-10-28
last reply Implementation for Intel Xeon Phi ? - James Amundson - 2014-01-14
Implementation for Intel Xeon Phi ?
Author:  Date: 2013-10-15 00:09

I'd like to know if there is any plan on extending this library to the Xeon Phi instruction set ?
And by the way, do you plan to extend your optimization books to this architecture ?


Kind regards,
Wilfried K.

Implementation for Intel Xeon Phi ?
Author: Agner Date: 2013-10-15 01:34
There is some confusion over which instruction set the Xeon Phi will use. The first manuals published in 2012 described an instruction set variously named "Knights Corner instruction set" and "Xeon Phi coprocessor instruction set". This instruction set has no CPUID bit so it is not possible to make a dispatcher for it. There are rumours that this instruction set is being replaced soon by the AVX-512 instruction set, which is very similar. Both instruction sets are backwards compatible, but they are not compatible with each other - differing by a single prefix bit even for otherwise identical instructions.

AVX-512 will run both on the MIC coprocessors and the mainstream CPUs. My plan is to support AVX-512 when it is available in mainstream CPUs and supported by the major compilers.

I think that the ABI standards (function calling conventions) are not completely fixed yet and AVX-512 has some problems with preparing for future extensions (see ) so it will take some time before everything is in place.

Implementation for Intel Xeon Phi ?
Author:  Date: 2013-10-28 04:36
Hi Wilfried, Agner,

I have started to write some vector classes for the MIC, sticking as much as possible to the design and interface of the other vector classes. I wrote the code for use in projects of my own, but I will be happy to contribute it if there is any interest.

It only supports basic operations on Vec8d, Vec16i, Vec8b and Vec16b for now, does not support dynamic dispatching (which I do not think is such an issue as the MIC is not binary compatible with mainline x86 anyways), is not production-quality and has no documentation. But it might be enough to get started and add the missing features along the way.

Hopefully, AVX-512 intrinsics should be close to those of Xeon Phi, even though the instruction encodings are different. I expect most of the work for supporting Xeon Phi would apply to AVX-512, with minor modifications for dispatching and adapting to ISA idiosyncrasies.


Implementation for Intel Xeon Phi ?
Author:  Date: 2014-01-14 11:18

I am very interested in getting vector class to work with the MIC (Phi) intrinsics. It sounds like your AVX-512 implementation would be a useful place to start. Would you be willing to share a copy with me?

Jim Amundson