Forwardcom: A project towards the ideal computer

[agner]

Forwardcom is a research project aiming at finding out what an ideal computer system would look like. Current microprocessors are bound by the legacy of old systems that were developed when priorities and technical limitations were very different from today. Learning from past mistakes and a long history of development, we are looking at a complete vertical redesign of instruction set, microarchitecture, ABI standard, compiler technology, and operating system to achieve a much more efficient and flexible computer design. The downside is, of course, that Forwardcom is not compatible with existing systems. Instead, it is designed to be forward compatible: Software that has been compiled for a particular Forwardcom CPU will be able to take advantage of later CPUs with larger vector registers without recompilation.

The Forwardcom instruction set combines the best from RISC and CISC to enable a highly efficient superscalar microprocessor pipeline. It includes a new highly efficient way of doing array loops with variable-length vector registers.

A website with further description of Forwardcom, detailed specifications, and a discussion forum is provided at https://www.forwardcom.info/.

I am seeking volunteers and cooperators for the Forwardcom project. If you are looking for an exciting topic for your university project - this is it.

[OptimisticLock]

Interesting research project!

In project's Github repo I was not able to find VHDL/Verilog files, but on the project's page it is mentioned that FPGA is under development. Are you planning to open source it as well?

[agner]

OptimisticLock wrote:

In project's Github repo I was not able to find VHDL/Verilog files

It is coming as soon as it has been developed to a stage where people can play with it. Right now, it needs input and output functions and a loader before you can do anything useful with it. The basic pipeline structure and integer instructions are working now. The soft core is coded in system verilog. I am using a Nexys Artix-7 100T FPGA board. The amount of system-specific code is minimized so that it can easily be ported to other FPGAs. I will need a bigger FPGA (Intel/Altera?) when larger vectors are implemented.

[McPh82]

This sounds like quite the great project, do you have an ETA for it, even a very generic one?

[agner]

@McPh82:

I expect to publish the first soft core this summer with the basic functionality. Keep an eye on www.forwardcom.info.

[shpalman]

It sounds like a very exciting project! Especially calculating the required stack size sounds will be very useful for me as I'm always having problems with making the stack bigger than necessary. Just the thing I need as I usually work with very big datasets. Is the release time any sooner? I have a bunch of free time nowadays and all day sitting at my property in Turkey and watching TV. I'd love to play around with it instead. Quarantine time is so boring..

[rajesh_g]

Hello. This sounds interesting. Are you still looking for folks to work on this project?

[agner]

rejesh_g wrote

This sounds interesting. Are you still looking for folks to work on this project?

Yes indeed. Please look at https://www.forwardcom.info.

The first softcore is working. You may start trying to run the examples in the emulator. If you have the FPGA board you can also try the examples in the softcore.