Memory load μops on P4/P4E microarchitecture

[cianfa72]

Hi,

reading your "The microarchitecture of Intel, AMD and VIA CPUs" latest update 2021-08-17, I would like to ask a question about section 5.4.

Starting from table 5.3 pag 55 it seems to me that memory load μops have to go on port 2 (single-speed load execution unit) and not on port 0 as said in the example 5.3 & 5.4 at page 56.

What do you think, does it makes sense ? Thank you.

[agner]

You are probably right. I don't remember much about the NetBurst architecture. Why do you care? NetBurst is long dead.

[cianfa72]

Why do you care? NetBurst is long dead.

Yes, it is. I am a newbie so my question was just to understand correctly how thing actually works.